CAD system for design and simulation of data converters

This work presents a simulation environment for the design of data converters using behavioral modeling in the MATLABSIMULINK platform. This environment utilizes a graphic user interface as a CAD tool to design and simulate different data converter architectures. Post-processing analysis tools are included for static and dynamic performance calculation. Introduction A data converter system contains many different parts, both digital and analog. For high resolution and for high conversion speed the complexity of systems becomes very high. In order to handle the global design it is therefore necessary to use a top-down approach. Starting from the specifications the architecture and the basic cells are defined and designed. The top-down approach must be followed by a bottom-up verification. If the required specifications are not met, there is an adjustment of individual block specifications, partitioning and architecture. The use of behavioral modeling significantly contributes to the design process: an accurate description of data converter behavior permits us to reduce the computational efforts translating into shorter simulation time. This paper describes a behavioral design environment addressing and supporting the following design steps: Selection of the architecture. Verification that the architecture is suitable. Estimation of the limits coming from each block. Simulation Environment Considerations Behavioral modeling is a problem that can be approached differently depending on the type of system that we want to simulate. In the case of mixed-signal systems, there are several languages or tools available that allow us to construct behavioral models. For instance, MATLAB has the SIMULINK toolbox in order to describe continuous and discrete systems in a graphical environment. The language has also provided the ability to develop in an easy way Graphic User Interfaces (GUI) to interact with the user in a graphical way. By using GUIs, the simulation environment becomes very intuitive and easy to use, as opposed to having to learn a set of commands and functions used in the software. Data converter simulation requires aside of the model itself, suitable input signal generators as well as post-processing tools for calculating the performance of the converter. The typical test signal used for characterizing data converters is a sinusoid or a ramp, which are easy to implement in any computer simulation environment. Also in many cases white noise sources are required. In fact, to properly model data converters, the thermal noise produced by resistors, switches and operational amplifiers has to be considered [l]. Since a data converter is a sampled data system, the aliasing effect of the thermal noise has to be taken into account. Once we have a model of the data converter and the proper input signals, a simulation of the circuit in the time domain provides a sequence of sampled data values. Then, a suitable processing of the raw output data permits us to evaluate the performance of the data converter. Typically, depending on the data converter architecture, we are interested in the linearity parameters (integral non-linearity or ZML and differential non-linearity or DNL) or in the resolution parameters (effective number of bits or Ne& signal-to-noise ratio or SNR and the signal-to-noise and distortion ratio or SNDR). Basic Blocks The most common data converter architectures used are the successive approximation algorithm, the flash approach, the sigma delta technique and all the algorithms that can be achieved with pipeline implementations. The basic blocks that are found in these architectures can also be found in the architectures for other conversion algorithms. The successive approximation converter commonly uses the charge redistribution architecture. This architecture has two basic blocks, a capacitive array controlled by switches and a comparator. The flash converter utilizes a passive resistive network to generate reference voltages and comparators. The sigma delta uses switched capacitor integrators, a comparator and complex digital circuitry. DAC and pipeline architectures use operational amplifiers (to achieve amplification by a given factor or to subtract voltages) and, again comparators. Therefore we will discuss the operational amplifier, and, in particular, its use in switched capacitor integrators, the comparator and the resistive array used in flash converters. Operational Amplijer Operational amplifiers are key components in data converter circuits. Quite often the performance of the operational amplifiers bounds the performance of a complete data converter. It is therefore necessary to include an accurate model of the operational amplifier, considering all of the non-idealities. Linear parameters such as finite gain and bandwidth are considered, as well as the non-linear effects, such as (hard) saturation and slew-rate. Since data converters are sampled-data systems, there are two possible approaches for modeling operational amplifiers. The first approach is based on traditional models of the operational amplifiers. The models consist of a set of equations and differential equations, which describe the behavior of the circuit. In the simulation, the transient behavior of the circuit is considered for each clock cycle. The simulation obviously allows us to obtain a good accuracy, but at the expense of a long simulation time. The second approach is based on models of the complete sub-circuit (for exa.mple an integrator or a buffer), which includes the operational amplifier. The model doesn't perform the time simulation each clock cycle but uses given equations that account for the global effect of 0-7803-7761-3/03/$17.00 02003 IEEE N-700 the operational amplifier non-idealities at the end of each clock cycle. Therefore, the use of relatively simple behavioral equations permits us to estimate the error produced at the output of the sub-circuit without going into the details of the transient behavior within the clock cycle. This approach is of course less accurate than the previous one, but much faster [2]. As an example, wc can considcr a switchcd capacitor (SC) integrator with transfer function _1 L H ( z ) = -. 1 z-’ Analog circuit implementations of the integrator deviate from this ideal behavior due to several non-ideal effects. One of the major causes of performance degradation in the SC integrators is the incomplete transfer of charge. This non-ideal effect is a consequence of the operational amplifier non-idealities, namely finite gain and bandwidth, slew rate and saturation voltages. Fig. 1 shows the model of the integrator including all the non-idealities, which will be considered in detail in the more complex circuits discussed in the next paragraphs. The MATLAB function that implements the Slew Rate. actuallv comorises Eons. (4). ( 5 ) . (6) . (7 ) and (8). Fig. 1 Simulink model of an SC integrator The op-amp of the integrator described by Eqn. (1) is ideal. However, the gain of any op-amp is finite and this causes a first limit. The effect is an integrator “leakage”: only a fraction of the previous output of the integrator is added to each new input sample. The transfer function of the integrator with leakage becomes